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CD74HC574E 74HC574 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Breadboard-Friendly DIP-20 IC (Pack of 10) in Kuwait CD74HC574E 74HC574 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Breadboard-Friendly DIP-20 IC (Pack of 10) in Kuwait CD74HC574E 74HC574 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Breadboard-Friendly DIP-20 IC (Pack of 10) in Kuwait CD74HC574E 74HC574 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Breadboard-Friendly DIP-20 IC (Pack of 10) in Kuwait CD74HC574E 74HC574 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Breadboard-Friendly DIP-20 IC (Pack of 10) in Kuwait CD74HC574E 74HC574 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Breadboard-Friendly DIP-20 IC (Pack of 10) in Kuwait CD74HC574E 74HC574 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Breadboard-Friendly DIP-20 IC (Pack of 10) in Kuwait CD74HC574E 74HC574 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Breadboard-Friendly DIP-20 IC (Pack of 10) in Kuwait

CD74HC574E 74HC574 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Breadboard-Friendly DIP-20 IC (Pack of 10)

KWD 6.500
– 1 +

Special Features

  • Buffered inputs, Common three-state output enable control, Three-state outputs Bus line driving capability
  • Typical propagation delay (clock to Q) = 15 ns at VCC = 5 V, CL = 15 pF, TA = 25℃ Fanout (over temperature range), Standard outputs: 10 LSTTL loads Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃, Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs, 2-V to 6-V operation
  • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V

Description

The CD74HC574E 74HC574 are octal D-type flip-flops with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the LOW to HIGH transition of clock (CP). The output enable (OE) controls the 3-state outputs and is independent of the register operation. When OE is HIGH, the outputs are in the high-impedance state.

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