Search

Home / Juried Engineering / Semiconductor Products
CD74HC4017E 74HC4017 High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs Breadboard-Friendly IC DIP-16 DIP16 (1 Piece) in Kuwait CD74HC4017E 74HC4017 High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs Breadboard-Friendly IC DIP-16 DIP16 (1 Piece) in Kuwait CD74HC4017E 74HC4017 High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs Breadboard-Friendly IC DIP-16 DIP16 (1 Piece) in Kuwait CD74HC4017E 74HC4017 High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs Breadboard-Friendly IC DIP-16 DIP16 (1 Piece) in Kuwait CD74HC4017E 74HC4017 High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs Breadboard-Friendly IC DIP-16 DIP16 (1 Piece) in Kuwait CD74HC4017E 74HC4017 High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs Breadboard-Friendly IC DIP-16 DIP16 (1 Piece) in Kuwait CD74HC4017E 74HC4017 High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs Breadboard-Friendly IC DIP-16 DIP16 (1 Piece) in Kuwait

CD74HC4017E 74HC4017 High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs Breadboard-Friendly IC DIP-16 DIP16 (1 Piece)

KWD 4.500

1 +

Special Features

  • The CD74HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs.
  • Fully Static Operation and Positive Edge Clocking, Buffered Inputs and Common Reset, Significant Power Reduction Compared to LSTTL Logic ICs
  • Typical fMAX = 50MHz at VCC =5V,CL = 15pF, TA =25°C and Significant Power Reduction Compared to LSTTL Logic Ics
  • Fanout (Over Temperature Range): Standard Outputs 10 LSTTL Loads, Bus Driver Outputs 15 LSTTL Loads, High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V
  • Wide Operating Temperature Range -55°C to 125°C and Balanced Propagation Delay and Transition Times

Description

The CD74HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE (CE) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except "0", low. The device can drive up to 10 low power Schottky equivalent loads.

Related Items


{"error":"Error","cart_limit":"You have too many items in your cart.","prod_limit":"You cannot add any more of this item"}